`ifndef UDLY
`define UDLY 1
`endif
module mem_mux__10(
  mem_req__0__valid,
  mem_req__0__ready,
  mem_req__0__we_n,
  mem_req__0__addr,
  mem_req__0__rdata,
  mem_req__0__wdata,
  mem__0__ce_n,
  mem__0__we_n,
  mem__0__addr,
  mem__0__rdata,
  mem__0__wdata,
  mem__1__ce_n,
  mem__1__we_n,
  mem__1__addr,
  mem__1__rdata,
  mem__1__wdata,
  clk,
  rstn
);
//parameter declare
//port declare
input mem_req__0__valid;
output mem_req__0__ready;
input mem_req__0__we_n;
input [31:0] mem_req__0__addr;
output [15:0] mem_req__0__rdata;
input [15:0] mem_req__0__wdata;
output mem__0__ce_n;
output mem__0__we_n;
output [31:0] mem__0__addr;
input [15:0] mem__0__rdata;
output [15:0] mem__0__wdata;
output mem__1__ce_n;
output mem__1__we_n;
output [31:0] mem__1__addr;
input [15:0] mem__1__rdata;
output [15:0] mem__1__wdata;
input clk;
input rstn;
//channel declare
//wire declare
logic __mem_sel_993;
logic __mem_sel_994;
logic [1:0] __mem_sel_idx_995;
logic __mem_sel_997;
logic __mem_sel_998;
logic [1:0] __mem_sel_idx_999;
logic __mux2req_ready_1002;
logic __t_1003;
logic __t_1004;
logic __ret_1006;
logic __index_1007;
logic __index_1008;
logic __valid_1009;
logic __cond_1010;
logic __cond_1011;
logic __valid_1012;
logic __cond_1013;
logic __cond_1014;
logic __ret_1016;
logic __index_1017;
logic __index_1018;
logic __valid_1019;
logic __cond_1020;
logic __cond_1021;
logic __valid_1022;
logic __cond_1023;
logic __cond_1024;
logic __cond_1025;
logic __cond_1026;
logic [31:0] __addr_t_1027;
logic __cond_1028;
logic [31:0] __mem_addr_t_1029;
logic __cond_1030;
logic __cond_1031;
logic [31:0] __addr_t_1032;
logic __cond_1033;
logic [31:0] __mem_addr_t_1034;
logic __cond_1035;
logic __cond_1036;
//port wire declare
wire mem_req__0__valid;
logic mem_req__0__ready;
wire mem_req__0__we_n;
wire [31:0] mem_req__0__addr;
logic [15:0] mem_req__0__rdata;
wire [15:0] mem_req__0__wdata;
logic mem__0__ce_n;
logic mem__0__we_n;
logic [31:0] mem__0__addr;
wire [15:0] mem__0__rdata;
logic [15:0] mem__0__wdata;
logic mem__1__ce_n;
logic mem__1__we_n;
logic [31:0] mem__1__addr;
wire [15:0] mem__1__rdata;
logic [15:0] mem__1__wdata;
wire clk;
wire rstn;
//register declare
//register init and update
reg [1:0] __mem_sel_idx_dly_996;
wire [1:0] ___mem_sel_idx_dly_996;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_996 <= #`UDLY 2'h0;
  end
  else begin
    __mem_sel_idx_dly_996 <= #`UDLY ___mem_sel_idx_dly_996;
  end
end

reg [1:0] __mem_sel_idx_dly_1000;
wire [1:0] ___mem_sel_idx_dly_1000;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_1000 <= #`UDLY 2'h0;
  end
  else begin
    __mem_sel_idx_dly_1000 <= #`UDLY ___mem_sel_idx_dly_1000;
  end
end

reg __mux2req_ready_dly_1001;
wire ___mux2req_ready_dly_1001;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mux2req_ready_dly_1001 <= #`UDLY 1'h0;
  end
  else begin
    __mux2req_ready_dly_1001 <= #`UDLY ___mux2req_ready_dly_1001;
  end
end

reg __round_1005;
wire ___round_1005;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_1005 <= #`UDLY 1'h0;
  end
  else begin
    __round_1005 <= #`UDLY ___round_1005;
  end
end

reg __round_1015;
wire ___round_1015;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_1015 <= #`UDLY 1'h0;
  end
  else begin
    __round_1015 <= #`UDLY ___round_1015;
  end
end

//assign logic
assign __t_1003 /* 64 */ = ((0<=mem_req__0__addr)&&(mem_req__0__addr<12287) /* 434 */ ) /* 64 */ ;
assign __mem_sel_993 /* 65 */ = (__t_1003 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign __t_1004 /* 64 */ = ((12288<=mem_req__0__addr)&&(mem_req__0__addr<24575) /* 434 */ ) /* 64 */ ;
assign __mem_sel_997 /* 65 */ = (__t_1004 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign ___round_1005 /* 330 */ = (1'b1 /* 331 */ )?((__ret_1006==2-1 /* 332 */ )?(0 /* 332 */ ):__ret_1006+1 /* 333 */  /* 333 */ ):__round_1005 /* 335 */  /* 334 */ ;
assign __index_1007 /* 337 */ = __round_1005 /* 337 */ ;
assign __index_1008 /* 339 */ = ((__round_1005+1)>=2 /* 340 */ )?(__round_1005+1-2 /* 341 */ ):__round_1005+1 /* 343 */  /* 342 */ ;
assign __cond_1010 /* 242 */ = 0==__index_1007 /* 242 */ ;
assign __cond_1011 /* 242 */ = 1==__index_1007 /* 242 */ ;
assign __valid_1009 /* 346 */ = ((({ 1{__cond_1010} }&((__mem_sel_993 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1011} }&((__mem_sel_994 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_1013 /* 242 */ = 0==__index_1008 /* 242 */ ;
assign __cond_1014 /* 242 */ = 1==__index_1008 /* 242 */ ;
assign __valid_1012 /* 346 */ = ((({ 1{__cond_1013} }&((__mem_sel_993 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1014} }&((__mem_sel_994 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_1006 /* 349 */ = (__valid_1009 /* 215 */ )?(__index_1007 /* 216 */ ):(__valid_1012 /* 215 */ )?(__index_1008 /* 216 */ ):(2 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_995 /* 80 */ = (__ret_1006 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_996 /* 81 */ = __mem_sel_idx_995 /* 81 */ ;
assign ___round_1015 /* 330 */ = (1'b1 /* 331 */ )?((__ret_1016==2-1 /* 332 */ )?(0 /* 332 */ ):__ret_1016+1 /* 333 */  /* 333 */ ):__round_1015 /* 335 */  /* 334 */ ;
assign __index_1017 /* 337 */ = __round_1015 /* 337 */ ;
assign __index_1018 /* 339 */ = ((__round_1015+1)>=2 /* 340 */ )?(__round_1015+1-2 /* 341 */ ):__round_1015+1 /* 343 */  /* 342 */ ;
assign __cond_1020 /* 242 */ = 0==__index_1017 /* 242 */ ;
assign __cond_1021 /* 242 */ = 1==__index_1017 /* 242 */ ;
assign __valid_1019 /* 346 */ = ((({ 1{__cond_1020} }&((__mem_sel_997 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1021} }&((__mem_sel_998 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_1023 /* 242 */ = 0==__index_1018 /* 242 */ ;
assign __cond_1024 /* 242 */ = 1==__index_1018 /* 242 */ ;
assign __valid_1022 /* 346 */ = ((({ 1{__cond_1023} }&((__mem_sel_997 /* 312 */ ))) /* 244 */ )|({ 1{__cond_1024} }&((__mem_sel_998 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_1016 /* 349 */ = (__valid_1019 /* 215 */ )?(__index_1017 /* 216 */ ):(__valid_1022 /* 215 */ )?(__index_1018 /* 216 */ ):(2 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_999 /* 80 */ = (__ret_1016 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_1000 /* 81 */ = __mem_sel_idx_999 /* 81 */ ;
assign __mux2req_ready_1002 /* 89 */ = (__mem_sel_idx_995==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):(__mem_sel_idx_999==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):((0 /* 88 */ ) /* 213 */ ) /* 218 */  /* 217 */  /* 217 */ ;
assign __cond_1025 /* 242 */ = __mem_sel_idx_dly_996==0 /* 242 */ ;
assign __cond_1026 /* 242 */ = __mem_sel_idx_dly_1000==0 /* 242 */ ;
assign mem_req__0__rdata /* 90 */ = ((({ 16{__cond_1025} }&((mem__0__rdata /* 87 */ ))) /* 244 */ )|({ 16{__cond_1026} }&((mem__1__rdata /* 87 */ ))) /* 246 */ ) /* 90 */ ;
assign ___mux2req_ready_dly_1001 /* 93 */ = __mux2req_ready_1002 /* 93 */ ;
assign mem_req__0__ready /* 94 */ = __mux2req_ready_1002 /* 94 */ ;
assign __cond_1028 /* 242 */ = (__mem_sel_idx_995==0)&&__mem_sel_993 /* 242 */ ;
assign __addr_t_1027 /* 111 */ = (({ 32{__cond_1028} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_1029 /* 112 */ = __addr_t_1027-0 /* 112 */ ;
assign mem__0__addr /* 113 */ = __mem_addr_t_1029[31:0] /* 113 */ ;
assign __cond_1030 /* 242 */ = (__mem_sel_idx_995==0)&&__mem_sel_993 /* 242 */ ;
assign mem__0__wdata /* 114 */ = (({ 16{__cond_1030} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_1031 /* 242 */ = (__mem_sel_idx_995==0)&&__mem_sel_993 /* 242 */ ;
assign mem__0__we_n /* 115 */ = (({ 1{__cond_1031} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__0__ce_n /* 116 */ = ((__mem_sel_idx_995==0)&&__mem_sel_993 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
assign __cond_1033 /* 242 */ = (__mem_sel_idx_999==0)&&__mem_sel_997 /* 242 */ ;
assign __addr_t_1032 /* 111 */ = (({ 32{__cond_1033} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_1034 /* 112 */ = __addr_t_1032-12288 /* 112 */ ;
assign mem__1__addr /* 113 */ = __mem_addr_t_1034[31:0] /* 113 */ ;
assign __cond_1035 /* 242 */ = (__mem_sel_idx_999==0)&&__mem_sel_997 /* 242 */ ;
assign mem__1__wdata /* 114 */ = (({ 16{__cond_1035} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_1036 /* 242 */ = (__mem_sel_idx_999==0)&&__mem_sel_997 /* 242 */ ;
assign mem__1__we_n /* 115 */ = (({ 1{__cond_1036} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__1__ce_n /* 116 */ = ((__mem_sel_idx_999==0)&&__mem_sel_997 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
//cell instance
endmodule
